The present invention relates to a technology which is especially effective if applied to a clock wiring and, more particularly, to a technology which is effective if used in a clock wiring of a semiconductor integrated circuit device such as a large scale integration semiconductor integrated circuit such as a processor having a number of functions, or a printed wiring.
In a semiconductor integrated circuit device, especially either a large scale integrated circuit such as a processor having a number of functions or a large scale integrated circuit (as will be shortly referred to as "LSI") capable of operating at a high speed, a number of flip-flops (as will be shortly referred to as "FF") have to be synchronously operated. At this time, in order to operate the circuit at a high speed, the rise/fall time of a clock has to be shortened to reduce the skew between the FFs. For this reduction, it is necessary to reduce the capacity of a clock wiring and to equalize the impedances, i.e., the resistances and capacities of the individual lines of the clock wiring.
In order to solve this problem, there is a disclosure in 15.4.1 to 15.4.4 of IEEE 1991 CUSTOM INTEGRATED CIRCUITS CONFERENCE.